View MAX5134AGUE_4767863.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-4209; Rev 2; 1/10
KIT ATION EVALU BLE AVAILA
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
General Description Features
16-/12-Bit Resolution Available in a 4mm x 4mm, 24-Pin TQFN Package or 16-Pin TSSOP Hardware-Selectable to Zero/Midscale DAC Output on Power-Up or Reset Double-Buffered Input Registers LDAC Asynchronously Updates DAC Outputs Simultaneously READY Facilitates Daisy Chaining High-Performance 10ppm/C Internal Reference Guaranteed Monotonic Over All Operating Conditions Wide +2.7V to +5.25V Supply Range Rail-to-Rail Buffered Output Operation Low Gain Error (Less Than 0.5%FS) and Offset (Less Than 10mV) 30MHz 3-Wire SPI-/QSPI-/MICROWIRE-/ DSP-Compatible Serial Interface CMOS-Compatible Inputs with Hysteresis Low-Power Consumption (ISHDN = 2A max)
MAX5134-MAX5137
The MAX5134-MAX5137 is a family of pin-compatible and software-compatible 16-bit and 12-bit DACs. The MAX5134/MAX5135 are low-power, quad 16-/12-bit, buffered voltage-output, high-linearity DACs. The MAX5136/MAX5137 are low-power, dual 16-/12-bit, buffered voltage-output, high-linearity DACs. They use a precision internal reference or a precision external reference for rail-to-rail operation. The MAX5134-MAX5137 accept a wide +2.7V to +5.25V supply-voltage range to accommodate most low-power and low-voltage applications. These devices accept a 3-wire SPITM-/QSPITM/MICROWIRETM-/DSP-compatible serial interface to save board space and reduce the complexity of optically isolated and transformer-isolated applications. The digital interface's double-buffered hardware and software LDAC provide simultaneous output updates. The serial interface features a READY output for easy daisy-chaining of several MAX5134-MAX5137 devices and/or other compatible devices. The MAX5134-MAX5137 include a hardware input to reset the DAC outputs to zero or midscale upon power-up or reset, providing additional safety for applications that drive valves or other transducers that need to be off during power-up. The high linearity of the DACs makes these devices ideal for precision control and instrumentation applications. The MAX5134- MAX5137 are available in an ultra-small (4mm x 4mm), 24-pin TQFN package or a 16-pin TSSOP package. Both packages are specified over the -40C to +105C extended industrial temperature range.
Ordering Information
PART MAX5134AGTG+ MAX5134AGUE+ MAX5135GTG+ MAX5135GUE+ MAX5136AGTG+ MAX5136GUE+ MAX5137GTG+ MAX5137GUE+ PINPACKAGE 24 TQFN-EP* 16 TSSOP 24 TQFN-EP* 16 TSSOP 24 TQFN-EP* 16 TSSOP 24 TQFN-EP* 16 TSSOP RESOLUTION (BITS) 16 Quad 16 Quad 12 Quad 12 Quad 16 Dual 16 Dual 12 Dual 12 Dual INL (LSB) 8 8 1 1 8 8 1 1
Applications
Automatic Test Equipment Automatic Tuning Communication Systems Data Acquisition Gain and Offset Adjustment Portable Instrumentation Power-Amplifier Control Process Control and Servo Loops Programmable Voltage and Current Sources
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Note: All devices are specified over the -40C to +105C operating temperature range.
Functional Diagrams, Pin Configurations, and Typical Operating Circuit appear at end of data sheet.
SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
ABSOLUTE MAXIMUM RATINGS
AVDD to GND...........................................................-0.3V to +6V DVDD to GND...........................................................-0.3V to +6V OUT0-OUT3 to GND ....................................-0.3V to the lower of (AVDD + 0.3V) and +6V REFI, REFO, M/Z to GND .............................-0.3V to the lower of (AVDD + 0.3V) and +6V SCLK, DIN, CS to GND ................................-0.3V to the lower of (DVDD + 0.3V) and +6V LDAC, READY to GND .................................-0.3V to the lower of (DVDD + 0.3V) and +6V Continuous Power Dissipation (TA = +70C) 24-Pin TQFN (derate at 17.5mW/C above +70C)....2222.2mW 16-Pin TSSOP (derate at 5.7mW/C above +70C).........457mW Maximum Current into Any Input or Output with the Exception of M/Z Pin .......................................50mA Maximum Current into M/Z Pin ...........................................5mA Operating Temperature Range .........................-40C to +105C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VGND = 0, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC ACCURACY (Notes 1, 2) Resolution Integral Nonlinearity (MAX5134/MAX5136) Integral Nonlinearity (MAX5135/MAX5137) Differential Nonlinearity Offset Error Offset-Error Drift Gain Error Gain Temperature Coefficient REFERENCE INPUT AVDD = 3V to 5.25V Reference-Input Voltage Range Reference-Input Impedance INTERNAL REFERENCE Reference Voltage Reference Temperature Coefficient Reference Output Impedance Line Regulation Maximum Capacitive Load CR VREFO TA = +25C (Note 5) 2.437 2.440 10 1 100 0.1 2.443 25 V ppm/C ppm/V nF VREFI AVDD = 2.7V to 3V 2 2 113 AVDD AVDD 0.2 V k GE (Note 4) -0.5 N INL INL DNL OE MAX5134/MAX5136 MAX5135/MAX5137 VREFI = 5V, AVDD = 5.25V (Note 3) TA = +25C -1 -1.0 -10 1 4 0.2 2 +0.5 +0.25 16 12 -8 2 +10 6 +1 +1.0 +10 Bits LSB LSB LSB mV V/C % of FS ppm FS/C SYMBOL CONDITIONS MIN TYP MAX UNITS
VREFI = 5V, AVDD = 5.25V Guaranteed monotonic (Note 4)
2
_______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VGND = 0, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DAC OUTPUT VOLTAGE (Note 2) Output Voltage Range DC Output Impedance Maximum Capacitive Load (Note 5) Resistive Load Short-Circuit Current Power-Up Time CL RL ISC AVDD = 5.25V AVDD = 2.7V From power-down mode 0.7 x DVDD 0.3 x DVDD VIN = 0 or DVDD -1 0.1 +1 10 DVDD - 0.5 0.4 1.25 5 0.5 25 10kHz 1Hz to 10kHz 120 18 25 -40 Series resistance = 0 Series resistance = 500 2 35 20 25 +40 No load 0.02 0.1 0.2 15 AVDD - 0.02 V nF F k mA s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5134-MAX5137
DIGITAL INPUTS (SCLK, DIN, CS, LDAC) (Note 6) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance DIGITAL OUTPUTS (READY) Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Major Code Transition Analog Glitch Impulse Output Noise Integrated Output Noise DAC-to-DAC Crosstalk SR tS Positive and negative 1/4 scale to 3/4 scale VREFI = AVDD = 5V settle to 2 LSB (Note 5) Code 0, all digital inputs from 0 to DVDD V/s s nV*s nV*s nV/Hz V nV*s VOH VOL ISOURCE = 3mA ISINK = 2mA V V VIH VIL IIN CIN V V A pF
_______________________________________________________________________________________
3
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VGND = 0, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS POWER REQUIREMENTS (Note 7) Analog Supply Voltage Range AVDD Digital Supply Voltage Range DVDD IAVDD Supply Current No load, all digital inputs at 0 or DVDD (MAX5134/MAX5135) IDVDD IAVDD Supply Current No load, all digital inputs at 0 or DVDD (MAX5136/MAX5137) IDVDD IAVPD Power-Down Supply Current No load, all digital inputs at 0 or DVDD IDVPD TIMING CHARACTERISTICS (Note 8) (Figure 1) Serial-Clock Frequency fSCLK SCLK Pulse-Width High tCH SCLK Pulse-Width Low tCL CS Fall-to-SCLK Fall Setup Time tCSS SCLK Fall-to CS-Rise Hold Time tCSH DIN-to-SCLK Fall Setup Time tDS DIN-to-SCLK Fall Hold Time tDH SCLK Fall to READY Transition tSRL (Note 9) CS Pulse-Width High tCSW LDAC Pulse Width tLDACPWL MIN 2.7 2.7 2.5 1 1.5 1 0.2 0.1 0 13 13 8 5 10 2 33 33 TYP MAX 5.25 AVDD 3.6 10 2.3 10 2 2 30 UNITS V V mA A mA A A
30
MHz ns ns ns ns ns ns ns ns ns
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Static accuracy tested without load. Linearity is tested within 20mV of GND and AVDD, allowing for gain and offset error. Codes above 2047 are guaranteed to be within 8 LSB. Gain and offset tested within 100mV of GND and AVDD. Guaranteed by design. Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < DVDD - 0.6V or VI > 0.5V. At VI = 2.2V with DVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input level compatible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing. Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without AVDD. Note 8: All timing specifications are with respect to the digital input and output thresholds. Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
COMMAND EXECUTED ON 24TH FALLING EDGE OF SCLK tCSW
CS
tCSS
SCLK
tCL
tCH
tCSH
tDS DIN X C7 C6 C5 D3 D2
tDH D1 D0 tSRL X
READY X = DON'T CARE.
Figure 1. Serial-Interface Timing Diagram
4 _______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX5134-MAX5137
MAX5134/MAX5136 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5134-MAX5137 toc01
MAX5134/MAX5136 INTEGRAL NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc02
MAX5134/MAX5136 INTEGRAL NONLINEARITY vs. TEMPERATURE
7 5 3 INL (LSB) 1 -1 -3 -5 -7 -9
MAX5134-MAX5137 toc03
9 6 3 INL (LSB) 0 -3 -6 -9 0 16384 32768 49152
9 7 5 3 INL (LSB) 1 -1 -3 -5 -7 -9
9
65536
2.7
3.2
3.7
4.2
4.7
5.2
-40
-20
0
20
40
60
80
100
DIGITAL INPUT CODE (LSB)
AVDD ( V )
TEMPERATURE (C)
MAX5134/MAX5136 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5134-MAX5137 toc04
MAX5134/MAX5136 DIFFERENTIAL NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc05
MAX5134/MAX5136 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX5134-MAX5137 toc06
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 49152
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
1.0
65536
2.7
3.2
3.7
4.2
4.7
5.2
-40
-20
0
20
40
60
80
100
DIGITAL INPUT CODE (LSB)
AVDD ( V )
TEMPERATURE (C)
MAX5134/MAX5136 OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc07
MAX5135/MAX5137 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.08 0.06 0.04 DNL (LSB) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -0.75 -1.00 0 1024 2048 3072 4096
MAX5134-MAX5137 toc08
MAX5135/MAX5137 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
0.75 0.50 INL (LSB) 0.25 0 -0.25 -0.50
MAX5134-MAX5137 toc09
10 8 6 OFFSET ERROR (mV) 4 2 0 -2 -4 -6 -8 -10 2.7 3.2 3.7 4.2 4.7
0.10
1.00
5.2
0
1024
2048
3072
4096
AVDD ( V )
DIGITAL INPUT CODE (LSB)
DIGITAL INPUT CODE (LSB)
_______________________________________________________________________________________
5
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
GAIN ERROR vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc10
OFFSET ERROR vs. TEMPERATURE
0 -0.1 OFFSET ERROR (mV) -0.2 -0.3 -0.4 -0.5 -0.6 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) VAVDD = 5.25V VREFI = 5V VAVDD = 2.7V VREFI = 2.5V 0.5 0.4 0.3 GAIN ERROR (%FS) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.7
GAIN ERROR vs. TEMPERATURE
MAX5134-MAX5137 toc11
0.084 0.082 GAIN ERROR (%FS) 0.080 0.078 0.076 0.074 0.072 0.070 -40 -20 0 20 40 VAVDD = 2.7V 60 80 100 VAVDD = 5.25V
3.2
3.7
4.2
4.7
5.2
AVDD ( V )
TEMPERATURE (C)
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc13
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5134-MAX5137 toc14
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE (POWER-DOWN MODE)
0.45 0.40 SUPPLY CURRENT (A) 0.35 0.30 0.25 0.20 0.15 0.10 TA = +25C TA = +105C TA = -40C
MAX5134-MAX5137 toc15
2500 2300 SUPPLY CURRENT (A) 2100 1900 1700 1500 1300 1100 900 2.7 3.2 3.7 4.2 4.7 VOUT_ = 0 (MAX5136/MAX5137) VOUT_ = VREFO (MAX5136/MAX5137) VOUT_ = VREFO (MAX5134/MAX5135) VOUT_ = 0 (MAX5134/MAX5135)
3000 IAVDD (MAX5134/MAX5135) 2500 SUPPLY CURRENT (A) 2000 1500 1000 500 0 IAVDD (MAX5136/MAX5137)
0.50
IDVDD
0.05 0 60 80 100 2.7 3.2 3.7 4.2 4.7 5.2
5.2
-40
-20
0
20
40
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
EXITING/ENTERING POWER-DOWN MODE
MAX5134-MAX5137 toc16
MAJOR CODE TRANSITION
MAX5134-MAX5137 toc17
SETTLING TIME UP
MAX5134-MAX5137 toc18
CH1
500mV/div
10mV/div
CH0 4s/div
500mV/div 1s/div 400ns/div
6
_______________________________________________________________________________________
MAX5134-MAX5137 toc12
0.086
500mV/div
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX5134-MAX5137
SETTLING TIME DOWN
MAX5134-MAX5137 toc19
CROSSTALK
MAX5134-MAX5137 toc20
DIGITAL FEEDTHROUGH
MAX5134-MAX5137 toc21
10mV/div
SCLK
5V/div
500mV/div
2V/div
VOUT_
50mV/div
400ns/div
4s/div
40ns/div
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
VAVDD = 5.25V, SCLK = 0Hz 3.5 SUPPLY CURRENT (nA) 3.0 2.5 2.0 1.5 1.0 0.5 0 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) 2.40 2.7
MAX5134-MAX5137 toc22
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX5134-MAX5137 toc23
REFERENCE VOLTAGE vs. TEMPERATURE
MAX5134-MAX5137 toc24
4.0
2.50
2.4405 2.4400 2.4395 VREFO (V) 2.4390 2.4385 2.4380
2.48
VREFO (V)
2.46
TA = +25C
2.44 TA = +105C
2.42
TA = -40C
2.4375 2.4370 -40
3.2
3.7
4.2
4.7
5.2
-20
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
DIGITAL SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
MAX5134-MAX5137 toc25
FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5134-MAX5137 toc26
OUTPUT VOLTAGE vs. OUTPUT CURRENT
2.45 2.40 OUTPUT VOLTAGE (V) 2.35 2.30 2.25 2.20 2.15 2.10 VAVDD = 3.3V VAVDD = 5V
MAX5134-MAX5137 toc27
3000 VAVDD = VDVDD = 5.25V DIGITAL SUPPLY CURRENT (A) 2500 UP 2000 1500 1000 500 0 0 1 2 3 4 5 DIGITAL INPUT VOLTAGE (V) DOWN
2.51 2.50 OUTPUT VOLTAGE (V) 2.49 2.48 2.47 2.46 2.45 2.44 2.43 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) INTERNAL REFERENCE EXTERNAL REFERENCE 2.500V
2.50
2.05 2.00 0 5 10 15 20 25 30 OUTPUT CURRENT (mA)
_______________________________________________________________________________________
7
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
REFERENCE INPUT RESPONSE vs. FREQUENCY
0
VOUT_ REF 500mV/div 500mV/div
MAX5134-MAX5137 toc30
FULL-SCALE REFERENCE FEEDTHROUGH
MAX5134-MAX5137 toc28
ZERO-SCALE REFERENCE FEEDTHROUGH
MAX5134-MAX5137 toc29
5
-5 VREF 500mV/div ATTENUATION (dB) -10 -15 -20 -25 -30 VOUT_ 10mV/div -35 -40 -45 20s/div 1 10 100 1000
0V VOUT 0V VREF
10,000
INPUT FREQUENCY (kHz)
POWER-UP GLITCH, ZERO SCALE, EXTERNAL REFERENCE
MAX5134-MAX5137 toc31
POWER-UP GLITCH, ZERO SCALE, INTERNAL REFERENCE
MAX5134-MAX5137 toc32
POWER-UP GLITCH, MIDSCALE, EXTERNAL REFERENCE
MAX5134-MAX5137 toc33
2V/div
2V/div
2V/div
VAVDD
VAVDD
VAVDD
1V/div VOUT_ 1V/div VOUT_ 1V/div VOUT_
POWER-UP GLITCH, MIDSCALE, INTERNAL REFERENCE
MAX5134-MAX5137 toc34
DC NOISE SPECTRUM, FFT PLOT
MAX5134-MAX5137 toc35
-40dBm 2V/div
VAVDD
10dB/div
1V/div VOUT_
2.5kHz/div
25kHz
8
_______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
Pin Description
PIN MAX5134 MAX5135 TQFN-EP 1 2, 5, 8, 11, 14, 17, 20, 23 3 4 6 7, 19 9 10 12 13 15 16 18 21 22 24 -- TSSOP 3 -- 4 5 6 7, 15 8 9 10 11 12 13 14 16 1 2 -- MAX5136 MAX5137 TQFN-EP 1 2, 5, 6, 8, 11, 13, 14, 17, 20, 23 3 4 -- 7, 19 9 10 12 -- 15 16 18 21 22 24 -- TSSOP 3 6, 11 4 5 -- 7, 15 8 9 10 -- 12 13 14 16 1 2 -- OUT0 N.C. DVDD READY OUT3 GND DIN CS SCLK OUT2 LDAC M/Z OUT1 REFO REFI AVDD EP Channel 0 Buffered DAC Output No Connection. Not internally connected. Digital Power Supply. Bypass DVDD with a 0.1F capacitor to GND. Active-Low Ready. Indicated configuration ready. Use READY as CS for consecutive part or as feedback to the C. Channel 3 Buffered DAC Output Ground Data In Active-Low Chip-Select Input Serial-Clock Input Channel 2 Buffered DAC Output Load DAC Input. Active-low hardware load DAC input. Power-Up Reset Select. Connect M/Z to DVDD to power up the DAC outputs to midscale. Connect M/Z to GND to power up the DAC outputs to zero. Channel 1 Buffered DAC Output Reference Voltage Output Reference Voltage Input. Bypass REFI with a 0.1F capacitor to GND when using external reference. Analog Power Supply. Bypass AVDD with a 0.1F capacitor to GND. Exposed Pad. Not internally connected. Connect to a ground or leave unconnected. Not intended as an electrical connection point. NAME FUNCTION
MAX5134-MAX5137
Detailed Description
The MAX5134-MAX5137 is a family of pin-compatible and software-compatible 16-bit and 12-bit DACs. The MAX5134/MAX5135 are low-power, quad 16-/12-bit, buffered voltage-output, high-linearity DACs. The MAX5136/MAX5137 are low-power, dual 16-/12-bit, buffered voltage-output, high-linearity DACs. The MAX5134-MAX5137 minimize the digital noise feedthrough from input to output by powering down the SCLK and DIN input buffers after completion of each 24bit serial input. On power-up, the MAX5134-MAX5137 reset the DAC outputs to zero or midscale, depending on the state of the M/Z input, providing additional safety for applications that drive valves or other transducers that need to be off on power-up. The MAX5134-MAX5137 contain a segmented resistor string-type DAC, a serial-in parallel-out shift register, a DAC register, power-on reset
(POR) circuit, and control logic. On the falling edge of the clock (SCLK) pulse, the serial input (DIN) data is shifted into the device, MSB first. During power-down, an internal 80k resistor pulls DAC outputs to GND.
Output Amplifiers (OUT0-OUT3)
The MAX5134-MAX5137 include internal buffers for all DAC outputs. The internal buffers provide improved load regulation and transition glitch suppression for the DAC outputs. The output buffers slew at 1.25V/s and drive up to 2k in parallel with 200pF. The analog supply voltage (AVDD) determines the maximum output voltage range of the device as AVDD powers the output buffers.
DAC Reference
Internal Reference The MAX5134-MAX5137 feature an internal reference with a nominal output of +2.44V. Connect REFO to REFI
9
_______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
when using the internal reference. Bypass REFO to GND with a 47pF (maximum 100pF) capacitor. Alternatively, if heavier decoupling is required, use a 1k resistor in series with a 1F capacitor in parallel with the existing 100pF capacitor. REFO can deliver up to 100A of current with no degradation in performance. Configure other reference voltages by applying a resistive potential divider with a total resistance greater than 33k from REFO to GND.
Serial Interface
The MAX5134-MAX5137 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSPs (Figures 2, 3). The interface provides three inputs, SCLK, CS, and DIN and one output, READY. Use READY to verify communication or to daisy-chain multiple devices (see the READY section). READY is capable of driving a 20pF load with a 30ns (max) delay from the falling edge of SCLK. The chip-select input (CS) frames the serial data loading at DIN. Following a chip-select input's high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial-clock input (SCLK). Each serial word is 24 bits. The first 8 bits are the control word followed by 16 data bits (MSB first), as shown in Table 1. The serial input register transfers its contents to the input registers after loading 24 bits of data. To initiate a new data transfer, drive CS high, keep CS high for a minimum of 33ns before the next write sequence. The SCLK can be either high or low between CS write pulses. Figure 1 shows the timing diagram for the complete 3-wire serialinterface transmission.
External Reference The external reference input features a typical input impedance of 113k and accepts an input voltage from +2V to AVDD. Connect an external voltage supply between REFI and GND to apply an external reference. Leave REFO unconnected. Visit www.maxim-ic.com/products/references for a list of available external voltage-reference devices. AVDD as Reference Connect AVDD to REFI to use AVDD as the reference voltage. Leave REFO unconnected.
Table 1. Operating Mode Truth Table*
24-BIT WORD CONTROL BITS MSB C7 C6 C5 C4 C3 0 0 0 0 0 C2 0 C1 0 C0 D15 D14 D13 D12 D11 D10 D9 0 X X X X X X X D8 X D7 X DATA BITS LSB D6-D0 X NOP No operation. Move contents of input to DAC registers indicated by 1's. No effect on registers indicated by 0's. Software clear. DESC FUNCTION
0
0
0
0
0
0
0
1
X
X
X
X
DAC DAC DAC DAC 3 2 1 0
X
X
LDAC
0
0
0
0
0
0
1
0
X
X
X
X
X
X
X
X
X
X
CLR
0
0
0
0
0
0
1
1
X
X
X
X
DAC DAC DAC DAC READY_EN 3 2 1 0 0 0 LIN 0 D8 0 D7
X
Power down DACs Power indicated by 1's. Control Set READY_EN = 1 to enable READY. Linearity Optimize DAC linearity. Write Write to selected input registers (DAC output not affected).
0 0
0 0
0 0
0 1
0
1
0
1
0
0
0
0
0 D6
DAC DAC DAC DAC D15 D14 D13 D12 D11 D10 D9 3 2 1 0
0
0
1
DAC DAC DAC DAC 1 D15 D14 D13 D12 D11 D10 D9 3 2 1 0 0 0 0 0 0 X X X X X X X
D8
D7
D6
Write to selected input Write- and DAC registers, through DAC outputs updated (writethrough). NOP No operation.
0
0
1
X
X
X
*For the MAX5136/MAX5137, DAC2 and DAC3 do not exist. For the MAX5135/MAX5137, D0-D3 are don't-care bits. 10 ______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
The MAX5134-MAX5137 digital inputs are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s) using the write command. To update the DAC registers, either pulse the LDAC input low to synchronously update all DAC outputs, or use the software LDAC command. Use the writethrough commands (see Table 1) to update the DAC outputs immediately after the data is received. Only use the writethrough command to update the DAC output immediately. The MAX5134/MAX5136 DAC code is unipolar binary with V OUT_ = (code/65,536) x V REF. The MAX5135/ MAX5137 DAC code is unipolar binary with VOUT_ = (code/4096) x VREF. See Table 1 for the serial interface commands. Connect the MAX5134-MAX5137 DVDD supply to the supply of the host DSP or microprocessor. The AVDD supply may be set to any voltage within the operating range of 2.7V to 5.25V, but must be greater than or equal to the DVDD supply.
MAX5134-MAX5137
Writing to the Devices
Write to the MAX5134-MAX5137 using the following sequence: 1) Drive CS low, enabling the shift register. 2) Clock 24 bits of data into DIN (C7 first and D0 last), observing the specified setup and hold times. Bits D15-D0 are the data bits that are written to the internal register. 3) After clocking in the last data bit, drive CS high. CS must remain high for 33ns before the next transmission is started. Figure 1 shows a write operation for the transmission of 24 bits. If CS is driven high at any point prior to receiving 24 bits, the transmission is discarded.
+5V
SCLK
SK SS READY* MISO*
MAX5134- DIN MAX5137
READY*
SO MICROWIRE PORT SI* SCLK SCK
MAX5134- DIN MAX5137
MOSI SPI/QSPI PORT
CS
I/O CS I/O
*THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICES *BUT MAY BE USED FOR TRANSMISSION VERIFICATION. *THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICES BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
Figure 2. Connections for MICROWIRE
Figure 3. Connections for SPI/QSPI
CS DIN SCLK 1 READY 1 READY 2 READY 3 2 3 4 20 21 22 23 24 1 2 3 4 5 21 22 23 24 1 2 3 4 5 21 22 23 24 SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA
Figure 4. READY Timing
______________________________________________________________________________________ 11
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
READY
Connect READY to a microcontroller (C) input to monitor the serial interface for valid communications. The READY pulse appears 24 clock cycles after the negative edge of CS (Figure 4). Since the MAX5134- MAX5137 look at the first 24 bits of the transmission following the falling edge of CS, it is possible to daisy chain devices with different command word lengths. READY goes high 16ns after CS is driven high. Daisy chain multiple MAX5134-MAX5137 devices by connecting the first device conventionally, then connect its READY output to the CS of the following device. Repeat for any other devices in the chain, and drive the SCLK and DIN lines in parallel (Figure 5). When sending commands to daisy-chained devices, the devices are accessed serially starting with the first device in the chain. The first 24 data bits are read by the first device, the second 24 data bits are read by the second device and so on (Figure 4). Figure 6 shows the configuration when CS is not driven by the C. These devices can be daisy chained with other compatible devices such as the MAX15500 output conditioner. To perform a daisy-chain write operation, drive CS low and output the data serially to DIN. The propagation of the READY signal then controls how the data is read by each device. As the data propagates through the daisy chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective CS input. To update just one device in a daisy chain, send the no-op command to the other devices in the chain. If READY is not required, write command 0x03 (power control) and set READY_EN = 0 (see Table 1) to disable the READY output.
Clear Command
The MAX5134-MAX5137 feature a software clear command (0x02). The software clear command acts as a software POR, erasing the contents of all registers. All outputs return to the state determined by the M/Z input.
Power-Down Mode
The MAX5134-MAX5137 feature a software-controlled individual power-down mode for each channel. The internal reference and biasing circuits power down to conserve power when all 4 channels are powered down. In power-down, the outputs disconnect from the buffers and are grounded with an internal 80k resistor. The DAC register holds the retained code so that the output is restored when the channel powers up. The serial interface remains active in power-down mode.
Load DAC (LDAC) Input
The MAX5134-MAX5137 feature an active-low LDAC logic input that allows the outputs to update asynchronously. Keep LDAC high during normal operation (when the device is controlled only through the serial interface). Drive LDAC low to simultaneously update all DAC outputs with data from their respective input registers. Figure 7 shows the LDAC timing with respect to OUT_. Holding LDAC low causes the input registers to become transparent and data written to the DAC registers to immediately update the DAC outputs. A software command can also activate the LDAC operation. To activate LDAC by software, set control word 0x01 and data bits A11-A8 to select which DAC to load, and all other data bits to don't care. See Table 1 for the data format. This operation updates only the DAC outputs that are flagged with a 1. DAC outputs flagged with a 0 remain unchanged.
C MOSI SCK SLAVE 1 SLAVE 2 SLAVE 3
MAX5134-
DIN MAX5137 SCLK READY CS
MAX5134-
DIN MAX5137 SCLK READY CS
MAX5134-
DIN MAX5137 SCLK READY CS
I/O
Figure 5. Daisy-Chain Configuration
12 ______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
TO OTHER CHIPS/CHAINS
CSm
C
CS1 CS SCLK DWRITE DREAD INT SLAVE 1 CS SCLK DIN
MAX5134- MAX5137
READY
SLAVE 2 CS SCLK DIN
MAX5134- MAX5137
READY
SLAVE N CS SCLK MAX15500 DIN DOUT ERROR READY
Figure 6. Daisy Chain (CS Not Used)
______________________________________________________________________________________
13
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
tLDACPWL LDAC tS OUT_ 2 LSB
Figure 7. Output Timing
Applications Information
Power-On Reset (POR)
On power-up, the input registers are set to zero, DAC outputs power up to zero or midscale, depending on the configuration of M/Z. Connect M/Z to GND to power the outputs to GND. Connect M/Z to AVDD to power the outputs to midscale. To guarantee DAC linearity, wait until the supplies have settled. Set the LIN bit in the DAC linearity register; wait 10ms, and clear the LIN bit.
Layout Considerations
Digital and AC transient signals on GND inputs can create noise at the outputs. Connect both GND inputs to form the star ground for the DAC system. Refer remote DAC loads to this system ground for the best possible performance. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5134-MAX5137 GND. Carefully lay out the traces between channels to reduce AC crosscoupling and crosstalk. Do not use wire-wrapped boards and sockets. Use shielding to improve noise immunity. Do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the MAX5134-MAX5137 package.
Unipolar Output
The MAX5134-MAX5137 unipolar output voltage range is 0 to VREFI. The output buffers each drive a load of 2k in parallel with 200pF.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function from a best fit straight line drawn between two codes. For the MAX5134/MAX5136, this best fit line is a line drawn between codes 3072 and 64,512 of the transfer function, once offset and gain errors have been nullified. For the MAX5135/MAX5137, this best fit line is a line drawn between codes 192 and 4032 of the transfer function, once offset and gain errors have been nullified.
Bipolar Output
Use the MAX5134-MAX5137 in bipolar applications with additional external components (see the Typical Operating Circuit).
Power Supplies and Bypassing Considerations
For best performance, use a separate supply for the MAX5134-MAX5137. Bypass both DVDD and AVDD with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device. Minimize lead lengths to reduce lead inductance. Connect both MAX5134-MAX5137 GND inputs to the analog ground plane.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is greater than -1 LSB, the DAC guarantees no missing codes and is monotonic.
Table 2. MAX5134/MAX5136 Input Code vs. Output Voltage
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT, VOUT_ VREF x (65,535/65,536) VREF x (32,768/65,536) = 1/2 VREF VREF x (1/65,536) 0
Table 3. MAX5135/MAX5137 Input Code vs. Output Voltage
DAC LATCH CONTENTS MSB 1111 1000 0000 0000 1111 0000 0000 0000 1111 0000 0001 0000 LSB XXXX XXXX XXXX XXXX ANALOG OUTPUT, VOUT_ VREF x (4095/4096) VREF x (2048/4096) VREF x (1/4096) 0
14
______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
Offset Error
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point where the MSB changes from low to high and all other bits change from high to low, or where the MSB changes from high to low and all other bits change from low to high. The duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse.
MAX5134-MAX5137
Gain Error
Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
Digital-to-Analog Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode.
Settling Time
The settling time is the amount of time required from the start of a transition, until the DAC output settles to the new output value within the converter's specified accuracy.
DC DAC-to-DAC Crosstalk
Crosstalk is the amount of noise that appears on a DAC output set to 0 when the other DAC is updated from 0 to AVDD
Digital Feedthrough
Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled. PROCESS: BiCMOS
Chip Information
Pin Configurations
OUT2** LDAC OUT1
N.C.
M/Z
TOP VIEW
N.C.
18 GND 19 N.C. 20 REF0 21 REFI 22 N.C. 23 AVDD 24
17
16
15
14
13 12 11 10 SCLK N.C. CS DIN N.C.
+
REFI 1 AVDD 2 OUT0 3 DVDD 4 READY 5 OUT3 6 16 REFO 15 GND 14 OUT1
MAX5134- MAX5137
*EP
MAX5134- MAX5137
13 M/Z 12 LDAC 11 OUT2** 10 SCLK 9 CS
9 8 7
GND 7 GND DIN 8
+
1 OUT0
2 N.C.
3 DVDD
4 READY
5 N.C.
6 OUT3**
TSSOP
THIN QFN (4mm x 4mm)
*EXPOSED PAD. **N.C. FOR THE MAX5136/MAX5137.
______________________________________________________________________________________
15
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
Functional Diagrams
AVDD
DVDD
GND
REFI
REFO
REFERENCE
M/Z
MAX5134 MAX5135
POR CONTROL LOGIC POWER-DOWN CONTROL
INPUT REGISTER
DAC REGISTER
12-/16-BIT DAC
OUT0 BUFFER
CS SCLK DIN INPUT REGISTER DAC REGISTER 12-/16-BIT DAC SERIAL-TOPARALLEL CONVERTER INPUT REGISTER DAC REGISTER 12-/16-BIT DAC OUT1 BUFFER
BUFFER
OUT2
INPUT REGISTER
DAC REGISTER
12-/16-BIT DAC
BUFFER
OUT3
READY
LDAC
16
______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
Functional Diagrams (continued)
MAX5134-MAX5137
AVDD
DVDD
GND
REFI
REFO
REFERENCE
M/Z
MAX5136 MAX5137
POR CONTROL LOGIC POWER-DOWN CONTROL
CS SCLK DIN SERIAL-TOPARALLEL CONVERTER
INPUT REGISTER
DAC REGISTER
12-/16-BIT DAC
OUT0 BUFFER
INPUT REGISTER
DAC REGISTER
12-/16-BIT DAC
BUFFER
OUT1
READY
LDAC
______________________________________________________________________________________
17
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs MAX5134-MAX5137
Typical Operating Circuit
DIGITAL POWER SUPPLY ANALOG POWER SUPPLY
100nF
100nF
100nF
DVDD M/Z LDAC CS SCLK DIN READY DAC
AVDD
OUT
MAX5134- MAX5137
REFO REFI 47pF
R1
R2
GND
NOTE: SHOWN IN BIPOLAR CONFIGURATION.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 TQFN-EP 16 TSSOP PACKAGE CODE T2444+4 U16+2 DOCUMENT NO. 21-0139 21-0066
18
______________________________________________________________________________________
Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs
Revision History
REVISION NUMBER 0 1 REVISION DATE 7/08 10/08 Initial release of MAX5134. Initial release of MAX5135/MAX5136/MAX5137. Added the TSSOP package to the Ordering Information table, Absolute Maximum Ratings section, and Pin Description table. Changed the Major Code Transition Analog Glitch Impulse parameter in the Electrical Characteristics table from 12nV*s (typ) to 25nV*s (typ). In the Typical Operating Characteristics; added "SCLK = 0Hz" to TOC22, changed TOC28 to "500mV/div" from "500mV"; and changed the title of TOC30 to "Reference Input Response vs. Frequency." Added a statement to the Internal Reference section regarding using a resistor in series. Changed the Functional Diagrams to show LDAC drawn to the DAC register. Replaced the Typical Operating Circuit to show the correct op amp. DESCRIPTION PAGES CHANGED -- 1-19 1, 2, 9 3
MAX5134-MAX5137
2
1/10
7, 8
10 16, 17 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
(c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX5134AGUE

	To Download MAX5134AGUE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .